High-performance memory systems using SiGe HBT BiCMOS Technology
Authors
Liu, Xuelian
ORCID
Loading...
Other Contributors
McDonald, John F. (John Francis), 1942-
Zhang, Tong
Hella, Mona Mostafa
Carothers, Christopher D.
Zhang, Tong
Hella, Mona Mostafa
Carothers, Christopher D.
Issue Date
2014-05
Keywords
Electrical engineering
Degree
PhD
Terms of Use
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
Full Citation
Abstract
A 128Kbit BiCMOS SRAM with a typical access time of 125ps was developed. The fast access time with moderate power dissipation has been achieved using following techniques: CML decoder, CML driver circuit, and bipolar sense amplifier. CMOS 6T memory cell is used to achieve the high packing density. The test result demonstrates that this SRAM macro can achieve working frequency of 4GHZ. This macro is especially useful for realizing ultrahigh speed, high density SRAMs which is used as L1 cache in the super computing processor.
Description
May 2014
School of Engineering
School of Engineering
Department
Dept. of Electrical, Computer, and Systems Engineering
Publisher
Rensselaer Polytechnic Institute, Troy, NY
Relationships
Rensselaer Theses and Dissertations Online Collection
Access
Restricted to current Rensselaer faculty, staff and students. Access inquiries may be directed to the Rensselaer Libraries.