CMOS transmitter blocks for mm-wave applications

Abstract

Recently, there has been a growing interest in the microwave and mm-wave circuits beyond 100GHz. With increasing demand for bandwidth in applications such as wireless video streaming, gaming and automotive radar, there is a need for front- end transceiver technology that can make it possible. Silicon CMOS has been the receiving major thrusts in millimetre-wave due to its low cost and integration ability. Commercial products are beginning to emerge at 60GHz for wireless short-range communication and at 77GHz in automotive radar. The focus of this work is to analyse and design the sub-blocks for a mm-wave transmitter at 200GHz using silicon CMOS technology. The target application is in high-data rate of more than 5Gbps for short range wireless communication at distances <1m.

The complete transmitter is fabricated in bulk 65nm CMOS and measured using on-wafer probe. The high power transmitter achieves close to 0.5mW of output power at 200GHz with a power consumption of 0.5W. This is the highest output power reported by a single transmitter structure designed using bulk 65nm silicon CMOS technology.

The combination of four power amplifiers along with the power combiner is followed by a frequency doubler to transmit high power millimetre-wave signal at 200GHz. A balanced passive frequency doubler with high input power saturation is designed for this purpose. The power amplifiers are preceded by a four stage common source driver amplifier to increase the gain of the transmitter chain. The inter-stage matching network for the driver amplifier is designed using transmission line stubs.

To further increase the output power, four power amplifiers are combined with a novel compact low loss power combiner. A mathematical model with coupled lines for the power combiner is presented and verified on a printed circuit board (PCB) at 5GHz. The power combiner achieves single-ended to two-way differential power division/combination with an insertion loss of less than 1 dB at 100GHz and occupies an area of 90×160μm 2 on-chip. The total output power from the four power amplifiers using the power combiner is increased to 16dBm at 100GHz.

Prior art in millimetre-wave in CMOS have focused on increasing the output power from the transmitter by employing antenna arrays that occupy large area on chip. In this work, to achieve high output power from the transmitter, a power amplifier is designed and optimized for high output power. Inter-stage matching network in the PA is realized using on-chip transformers to reduce chip area. A transformer model to understand the loss mechanisms and to speed up simulation time is presented. The fully differential power amplifier is fabricated in 65nm bulk CMOS and is measured by on-wafer probing. The PA achieves a peak output power (P sat )=11.7dBm with a gain of 13dB at 100GHz.