Quantitative analysis and modeling of 3-D TSV-based power delivery architectures

Abstract

In this work, a hybrid simulation approach is adopted as the major approach along with analytical method to examine 3-D power networks. Combining electromagnetic (EM) tools and circuit simulators, the hybrid approach is able to analyze and model micrometer-scale components as well as centimeter-scale power delivery system with high accuracy and efficiency. The parasitic elements of the components on the power delivery can be precisely modeled by full-wave EM solvers. Stack-up circuit models for the 3-D power delivery networks (PDNs) are constructed through a partition and assembly method. With the efficiency advantage of the SPICE circuit simulation, the overall 3-D system power performance can be analyzed and the 3-D power delivery architectures can be evaluated in a short computing time.

Transient analysis is performed to simulate the simultaneous switching noises (SSN) under a quasi-real current pattern (i.e., transition from idle state to active state with 3-GHz switching). The transient voltage noise has distinct frequency features that are associated with different PDN levels/components.

The key 3-D PDN components (i.e., TSV, decoupling capacitor, etc.) and design parameters (i.e., TSV number, arrangement, IC number/type, etc.) are systematically analyzed to provide design implications and understanding of the trade-off in the 3-D PDN architectures.

The PDN impedance is a critical criterion to evaluate the PDN performance since it describes the frequency response of the entire power delivery system. The PDN impedance is simulated combining the on-chip components of the 3-D chip stack (e.g., TSV, µ-bump, and power grid) and off-chip components (e.g., package, board, and voltage regulator module). The comparison among different types of 3D-PDN impedance reveals the characteristics of the 3D-PDN and helps to understand the 3D-PDN behavior in different frequency regions.

As 3-D technology enters the commercial production stage, it is critical to understand different 3-D power delivery architectures on the stacked ICs and packages with through-silicon vias (TSVs). Appropriate design, modeling, analysis, and optimization approaches of the 3-D power delivery system are of foremost significance and great practical interest to the semiconductor industry in general.

Based on fundamental physics of 3-D integration components, the objective of this thesis work is to quantitatively analyze the power delivery for 3D-IC systems, develop appropriate physics-based models and simulation approaches, understand the key issues, and provide potential solutions for design of 3D-IC power delivery architectures.

The major power delivery issues are the voltage drop (IR drop) and voltage noise. With a baseline of 3-D power delivery architecture, the on-chip PDNs of TSV-based chip stacks are modeled and analyzed for the IR drop and AC noise. The basic design factors are evaluated using the hybrid approach, such as the number of stacked chips, the number of TSVs, and the TSV arrangement. Analytical formulas are also developed to evaluate the IR drop in 3-D chip stack in good accordance with the simulation results.