High-speed serial circuits using SiGe HBT BiCMOS technology

Abstract

High speed serial communication continues to be in high demand to keep up with the ever-increasing digital communication circuits, which in all practically, leads to higher demand of security. The goal of this research is to explore high speed serial data transmission and scrambling capability utilizing state-of-the-art 130nm and 90nm SiGe BiCMOS Technology. A novel clock distribution technique using clock doublers in close proximity to sub-circuits to achieve high speed, low noise, and low power is explored. Three components are designed and developed: Scrambler, Serializer (Transmitter), and Deserializer (Receiver).

A complete SERDES circuit utilizing both the serializer and deserializer on chip including a wireline channel has been fabricated and tested. This has dimensions of 4 mm by 2.3 mm and consume about 2.7 A at 3.4 V, dissipating 9.2 W.

The 1:4 deserializer circuit has the dimensions of 1.4 mm by 1.5mm and utilizes a power supply voltage of 3.4 V consuming 0.97 A, and dissipating 3.3W. It utilizes clock data recovery circuit which includes a binary phase detector, charge pump, low-pass filter, and a VCO with hybrid tuning capability. It also utilizes three sets of data flip-flops as the phase detector and first demultiplexor stage which are clocked from three active-type clock doublers, and two sets of flip flops for last demux stage.

The 4:1 serializer circuit has the dimensions of 2.3 mm by 2.3 mm and utilizes a power supply voltage of 3.4 consuming 1.7 A, and dissipating 5.78 W. It utilizes a 5-latch MUX design, high speed self-bias latch, 210-1 PRBS, and three active-type clock doublers.

The scrambler circuit has the dimensions 3.0 mm by 2.0 mm and utilized two power supply voltages consuming 2.4 A at 3.4 V and 0.08 A at 5.5 V, dissipating a total of 8.6 W. It utilizes 2 sets of 5-latchs at 5.5V, a 4-parrelel output LFSR with 2:1 multi-plexors, and 4 passive-type clock doublers.