Serial code acceleration with single-isa asymmetric multi-core processor
Authors
Raman, Srikumar
ORCID
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Other Contributors
McDonald, John F. (John Francis), 1942-
Zhang, Tong
Schoch, Paul M.
Carothers, Christopher D.
Zhang, Tong
Schoch, Paul M.
Carothers, Christopher D.
Issue Date
2015-12
Keywords
Electrical engineering
Degree
PhD
Terms of Use
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
Full Citation
Abstract
In the current era, the computing industry has become firmly entrenched in the multi-core approach. Aided by Moore's law and technology scaling, the number of cores on state-of-the art multi-cores has been steadily increasing. While this has aided parallel computing efforts to a large extent, very little has been done to improve serial code performance in the last decade. This research explores the use of a high clock rate core, to accelerate serial sections of the workload, in conjunction with a set of slower cores that operate in parallel that continue to take advantage of the parallelizability of the workload.
Description
December 2015
School of Engineering
School of Engineering
Department
Dept. of Electrical, Computer, and Systems Engineering
Publisher
Rensselaer Polytechnic Institute, Troy, NY
Relationships
Rensselaer Theses and Dissertations Online Collection
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