dc.rights.license | Restricted to current Rensselaer faculty, staff and students. Access inquiries may be directed to the Rensselaer Libraries. | |
dc.contributor | Zhang, Tong | |
dc.contributor | Le Coz, Yannick L. | |
dc.contributor | Saulnier, Gary J. | |
dc.contributor | Carothers, Christopher D. | |
dc.contributor.author | Zhang, Xuebin | |
dc.date.accessioned | 2021-11-03T08:47:17Z | |
dc.date.available | 2021-11-03T08:47:17Z | |
dc.date.created | 2017-05-18T14:41:47Z | |
dc.date.issued | 2016-05 | |
dc.identifier.uri | https://hdl.handle.net/20.500.13015/1922 | |
dc.description | May 2016 | |
dc.description | School of Engineering | |
dc.description.abstract | The steady bit cost reduction over the past decade has enabled NAND flash memory to play an increasingly important role in numerous applications from enterprise data centers to portable mobile devices. As the society enters the big data era, it is imperative to take advantage of low-cost, high-speed NAND flash memory to optimize the design and implementation of storage systems. Nevertheless, bit cost reduction of flash memory inevitably couples with raw storage reliability degradation and limited lifespan, which causes serious challenges and meanwhile brings opportunities for research innovations. This thesis presents design solutions that address these challenges for different application domains, which share the common theme of cohesively exploiting domain-specific system-level characteristics and flash memory design. | |
dc.description.abstract | storage. Experiments show that the developed design solution can reduce up to 80% write stress with almost negligible latency overhead. | |
dc.description.abstract | a prototyping file system to empirically verify the realization of transparent compression with zero read amplification. This thesis further demonstrates that the OS/Apps footprint can be reduced by up to 39% on a Nexus 7 tablet installed with Android 5.0, and Apps' launching time could be | |
dc.description.abstract | reduced by over 26%. Through ASIC (application-specific integrated circuit) design, this thesis shows that the proposed computer architecture level design solution can eliminate the decompression latency overhead with very small implementation cost. | |
dc.description.abstract | memory by more than 60% for video data storage. | |
dc.description.abstract | Aiming to facilitate the use of flash memory for video caching in content delivery systems, this thesis presents a set of orthogonal design techniques that leverage the characteristics of video coding to optimize flash memory fault tolerance. Motivated by the observation that general-purpose flash-based storage devices provide a finer-than-necessary data access granularity for video storage, this thesis presents a more flexible ECC (error correction coding) scheme to improve the lifetime of flash-based video storage. On the other hand, this thesis further explores control-stream assisted transcoding strategy to reduce the video data storage space overhead. Moreover, a reliability-aware data placement strategy is presented to further eliminate the storage overhead of control stream. The developed techniques can improve the overall lifetime of flash | |
dc.description.abstract | Transparent compression is also an effective means to reduce the data amount written into flash memory. Nevertheless, transparent compression is not widely applied in commercial mobile devices because of the latency penalty. In conventional practice on implementing transparent compression, read latency overhead comes from two aspects, including read amplification and decompression computational latency. This thesis presents cross-layer design solutions to eliminate the read amplification at the file system level and eliminate the computational latency overhead at the computer architecture level. To demonstrate its practical feasibility, this thesis first implements | |
dc.description.abstract | In computing systems, data being written to the storage devices could exhibit strong temporal redundancy, especially for hot data that are frequently updated over a short period. Such temporal data content redundancy leads to excessive write amplification, which essentially wastes the limited lifetime of flash memory. Due to the out-of-place update mechanism of NAND flash memory, this could further leads to large storage space utilization. To alleviate this storage space waste and improve the lifetime, this thesis presents an opportunistic in-place delta compression for NAND flash memory. Leveraging the progressive-programming feature of SLC-mode flash memory pages, this thesis proposes a design solution that can apply delta lossless compression to minimize write amplification caused by temporal redundancy and meanwhile simplify the data management of deltas | |
dc.language.iso | ENG | |
dc.publisher | Rensselaer Polytechnic Institute, Troy, NY | |
dc.relation.ispartof | Rensselaer Theses and Dissertations Online Collection | |
dc.subject | Computer Systems engineering | |
dc.title | Domain-specific solid-state data storage systems design | |
dc.type | Electronic thesis | |
dc.type | Thesis | |
dc.digitool.pid | 178110 | |
dc.digitool.pid | 178111 | |
dc.digitool.pid | 178112 | |
dc.rights.holder | This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author. | |
dc.description.degree | PhD | |
dc.relation.department | Dept. of Electrical, Computer, and Systems Engineering | |