High speed capacitance extraction in integrated circuits using a stochastic random-walk algorithm

Abstract

This thesis presents the basic development and subsequent application of a novel stochastic algorithm for high-speed capacitance extraction in complex integrated circuits. The algorithm is an optimized variant of the Floating Random-Walk Method. Its overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical error cancellation, selective integration over electrode Guassian surfaces and direct capacitance-matrix evaluation. Computational experiments were carried out to demonstrate the improvement in execution time and accuracy in calculating capacitance in complex integrated circuits. The underlying premise of this thesis is to show that stochastic techniques are viable alternatives to deterministic techniques for high speed capacitance extraction in integrated circuits, especially as we move towards Ultra Large Scale Integration (ULSI) and Giga Scale Integration (GSI).