CAD for RSFQ design and applications to phase locked loops

Abstract

The HDL created for this research is named the hierarchical Single-Flux-Quantum Hardware Description Language Cadence (hSFQHDLC). This HDL allows for the automated verification and optimization of superconducting circuit schematics in a Cadence design environment.

The JJ PLL created for this research is designed to be manufactured in the MIT Lincoln Labs SFQ5ee process. A phase-frequency detector, divider chain, and voltage-controlled oscillator where designed and the schematic of these designs where verified and optimized using hSFQHDLC. The phase-frequency detector and divider chain where submitted for manufacture under the SFQ5ee process, measuring 259.05 x 120.9 uM and 109.15 x 13.95 uM respectively.

The goal of this research is to create a new Hardware Description Language (HDL) to allow for Superconducting JJ circuit verification and optimization. The test platform for this HDL is the design of a high speed, stable 64 GHz clock source via a superconducting JJ multiplying Phase Locked Loop (PLL). The created HDL is applied to the Phase Locked Loop (PLL) design for verification and optimization, providing an on-chip clock for superconducting circuits using Josephson Junctions (JJ).

One solution to this power problem is to construct computing solutions using superconducting Josephson Junctions (JJ). Superconducting circuits have the potential to operate at very high clock speeds with very low power consumption. Unfortunately, there currently does not exist a reliable, high speed on-chip clock source for these Superconducting JJ systems. To create such a clock source, we will need to design the circuit in a JJ system and then verify and optimize it. The verification and optimization step require the creation of a Hardware Description Language (HDL) for Superconducting JJ Systems.

The need and demand for large-scale and high-speed computing in the United States, and the rest of the world, grows every year. The supercomputers and data-centers that serve this need will use a larger and larger percentage of the world’s power as this demand increases. A solution must be found to lower the power requirements of these computing resources while maintaining the current clock speeds before these power requirements exceed the world’s available power capabilities.