Integrable quasi-vertical gallium nitride power UMOSFETs and their application to monolithic optoelectronic integration

Abstract

Monolithic optoelectronic integration provides a compact, high speed and cost-effective solution for visible light communication (VLC) by reducing parasitics between light-emitting diode (LED) and its driver field-effect transistor (FET). Gallium nitride enables optoelectronic integration on the same material system, because it is not only irreplaceable in illumination-grade LEDs, but also under development in the power switching applications. Compared with other GaN power FETs, quasi-vertical UMOSFETs provide sufficient threshold voltage and process-compatibility with LEDs. The goal is to develop integrable, high-voltage quasi-vertical GaN power UMOSFETs, as well as prototype GaN quasi-vertical UMOSFET/LED monolithic integration for light-emitting integrated circuits.

The GaN UMOSFET/LED optoelectronic integrated pairs are demonstrated using selective epi removal approach. The fabrication processes combine integrable LEDs with integrable quasi-vertical UMOSFETs. Functional GaN quasi-vertical power UMOSFET/LED pairs are the first demonstration in the world. The controllable modulation of LED current and light output power (LOP) with varying VDD and VGS of the integrated UMOSFET is verified. At VGS = 36 V and VDD = 20 V, LOP of 4.9 W/cm2 (or 6.0 mW) is obtained on an integrated device with a 350μm×350μm LED. The trade-off between FET area coverage and FET power dissipation is studied; a tested device with the best trade-off has FET/LED area ratio of 24% and FET/LED power ratio of 56%. The integrated device with a 3-LED chain driven by one FET is functional and exhibits an optical bandwidth of 9 MHz in the high-frequency modulation test. In addition, the integrated LED turns on at 5 V, with peak EQE of 2.4% and peak wavelength of 484 nm.

The integrable, high-voltage quasi-vertical GaN power UMOSFETs are designed and experimentally demonstrated. Hexagonal cells are used in the layout to obtain m-plane MOS gate sidewalls. Essential processes of gate trench and drain trench etching are developed. Fabricated devices exhibit smallest Ron,sp of 23 mΩ-cm2 and highest ID,sat of 295 A/cm2 in an 11-μm cell-pitch device. By applying a 2D-array resistance network model in devices with different number of cell columns, the unit hexagonal hexagonal-cell Ron,sp of 8.5 mΩ-cm2 and buried-layer RBL,□ of 223 Ω/□ are extracted. Performance of open-cell and closed-cell geometries are compared: the former has smaller Ron,sp, higher breakdown voltage (BV) but larger off-state leakage current than the latter. BV of open and closed-cell design are 208 V and 89 V, respectively. In addition, performance of various GaN normally-off power transistors are compared by calculation and simulation; GaN vertical UMOSFETs outperform lateral HEMTs and are comparable to CAVETs at higher voltage ratings such as 1200 V in terms of smaller Ron,sp, shorter switching time and smaller switching energy loss.

Furthermore, GaN MIS capacitors are experimentally studied. It is found that ALD SiO2 is more suitable as gate dielectrics than LPCVD Si3N4 in terms of smaller Qit and smaller leakage current. Pyroelectric polarization effect is found on several (0001) GaN MIS capacitors with different dielectrics (SiO2, Al2O3 and Si3N4), indicating the general nature of this phenomenon. Study on temperature-dependent GaN/SiO2 interface trap properties shows that higher temperature reduces trap time constants, allowing observation of deeper level traps.