Development of a methodology for automatic placement and routing of sfq circuit designs and an associated standard cell library

Abstract

Since the early 1990s, Single flux quantum (SFQ) logic has been wielded as a worthy alternative to power efficient high performance computing. Many significant circuit demonstrations have been made in this technology, such as single gate clock speeds of upto 750 GHz, 8-32 bit adders, multipliers, ALU at clock speeds of 20 to 30 GHz and Analog-to-digital converters with sample rates of 40 GHz , all by several research efforts. However, this new technology has presented some design challenges as well: SFQ does not have the same density as CMOS circuits. They still need an effective power efficient solution for data storage , and most importantly do not yet have a universally accepted optimal circuit design approach.

Further in this work, a novel Auto Placement and Routing (APR) methodology is proposed for HDL based designs utilizing an asynchronous SFQ cell library. The APR methodology hinges on utilizing the commercial APR tool Innovus, that is primarily intended for routing CMOS cells, and modifying the input parameters so as to make the software route and place SFQ cells as well. A standard cell library was made based on a fabricated and functionally tested asynchronous OR gate. The APR methodology is able to perform automatic power line routing and pass Layout vs Schematic (LVS) and Design Rule Check (DRC) on the finished layout. Finally, through use of intermediate Python scripts,information about the Passive Transmission Lines (PTL) laid out in the final layout are extracted and accounted for in analog simulations as verification of the functionality for the back annotated design.

Then, the place and route methodology is extended to HDL designs comprising memory by adding a Non Destructive Readout (NDRO) Flip Flop to the SFQ cell library. Three HDL designs were passed through this place and route methodology : a 4-bit ALU, 4-bit Register File and a 11-bit Processor operating on 4-bits of word. All three designs were successfully converted to layouts and had functionality verified through analog simulations with back annotated interconnect wire lengths. This has been discussed at length in published paper "An Automatic Placement and Routing Methodology for Asynchronous SFQ Circuit Design" (DOI:10.1109/TASC.2019.2942263)

More specifically, the inherent synchronous nature of all logic gates generally used in this technology makes it tedious to obtain a direct synthesis and place and route process from Behavioral Hardware Description Language (HDL) designs. The extensive use of clock trees as a result of every gate operation being pipelined often results in jitter problems and interconnect delays on the order of 100ps. Thus, although, there have been significant recent strides in research in developing open source software to integrate an automated design flow into this technology, practical fabricated circuits have still mostly relied on intensive human design intervention to maintain operational feasibility.

In light of such design challenges, a fundamentally different approach to logic gate design in SFQ has been proposed in the current work so as to make them asynchronous in nature through local self timing. This design change now makes it possible to utilize established and commercial EDA tools from vendors such as Synopsys and Cadence into following the automated design flow from synthesis to place and route in SFQ.