A contemporary assessment of the lateral silicon-germanium bipolar transistor

Abstract

The goal of this research is to develop a design environment that can enable the creation of digital circuitry for the proposed technology.

Tools have been verified and tested through the creation of a CML standard cell library, which contains 11 logical functions. The cells demonstrate picosecond rise and fall times, low power dissipation, and greatly reduced area when benchmarked against existing CML designs. The standard cells were demonstrated through the creation of a 30 GHz 32-bit Kogge Stone adder carry chain. The 32-bit Kogge Stone Adder Carry Chain created for this research is designed to be compatible with a contemporary CMOS process. Compared to other similar state-of-the-art designs, the circuit has nearly 1/200th of the power dissipation of other CML circuits, and measures to about 35x35 um.

The design environment created for this research has a majority of the features available in a contemporary PDK. Verification tools including LVS, DRC, and PEX have been supported and tested. In addition, advanced EDA tools, including automated placement and routing, have been enabled to support VLSI design. Additional algorithms have been created to support synthesis and automated design with common mode logic.

This deck will be used to demonstrate the proposed device as an enhancement to CMOS. This work explores the design, characteristics, implementation, and utility of Silicon-Germanium Lateral Heterojunction Bipolar Transistors (LHBT). At the device level, the major findings were THz peak fT/fmax performance, high speed operation in saturation, lower power dissipation enabled by advanced scaling, high drive currents, and CMOS-like density. A device is presented with operating frequencies exceeding 1THz. These results were used to develop a compact model, known as a MEXTRAM, which enables exploration of much larger circuits compared to what is achievable in TCAD.

As CMOS begins to reach fundamental limits of scaling, there has been a growing need for novel computing technologies. One such device is the lateral Silicon Germanium heterojunction bipolar which has immense promise to expand the capabilities of CMOS. The lateral bipolar transistor is able to achieve the THz speeds of the vertical bipolar transistor with a much lower power and area footprint. In addition, the FET-like structure of the lateral device allows for integration into contemporary CMOS processes.