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dc.rights.licenseRestricted to current Rensselaer faculty, staff and students. Access inquiries may be directed to the Rensselaer Libraries.
dc.contributorZhang, Tong
dc.contributorFranklin, W. Randolph
dc.contributorLe Coz, Yannick L.
dc.contributorCarothers, Christopher D.
dc.contributor.authorChen, Xubin
dc.date.accessioned2021-11-03T09:22:45Z
dc.date.available2021-11-03T09:22:45Z
dc.date.created2021-02-22T15:34:23Z
dc.date.issued2020-08
dc.identifier.urihttps://hdl.handle.net/20.500.13015/2635
dc.descriptionAugust 2020
dc.descriptionSchool of Engineering
dc.description.abstractTherefore, this thesis focuses on mitigating the impact of compaction while keeping the data structures and algorithms in existing KV stores completely intact. Instead of directly reducing the write amplification, this thesis applies the simple memory/storage tiering concept to mitigate the impact of compaction at the cost of larger write-ahead log (WAL) and host memory capacity usage. This thesis presents design approaches to effectively reduce the WAL size and memory cost. This thesis integrates the developed solution into RocksDB by only adding about 1,200 lines of code, without touching its core data structure and algorithm. Using 100GB and 1TB datasets as test vehicles, this thesis carries out experiments with db bench and YCSB workloads, and the results show that the modified RocksDB can improve the ops/s by up to 100.7% and meanwhile reduce the 99-percentile tail latency by up to 82%.
dc.description.abstractThe industry has been fully embracing NAND flash memory and emerging non-volatile memory (NVM) technologies (e.g. 3D XPoint and ReRAM) to innovate the memory and data storage hierarchy in computing systems. Although continuous technology scaling and transition from 2D to 3D fabrication have successfully sustained the memory bit cost reduction over the years, they increasingly cause more and more severe reliability and speed performance degradation. This thesis presents a variety of system architecture design solutions that can improve the speed performance and reliability of solid-state data storage devices built upon highly scaled flash memory and emerging NVM technologies.
dc.description.abstractThis thesis first studies the potential of leveraging a very small amount (i.e., a few MBs) of capacitor-powered write buffer inside today’s commercial solid-state drives (SSDs) to reduce the total flash memory write traffic. This thesis presents a set of design strategies across the application and storage device levels in order to maximize the utilization of the very small intra-SSD write buffer. The presented design strategies are mainly suitable for applications that involve logging/journaling operations. Applications could treat the intra-SSD write buffer as either a write-back cache to directly absorb write traffic, or a staging area to enable application-level data reduction. Using two popular open-source relational databases (i.e., MySQL and PostgreSQL) and the widely deployed filesystem ext4 as the test vehicles, detailed case studies and experiments are carried out. The results have well demonstrated the promising potential of the proposed design strategies on reducing the total flash memory write traffic.
dc.description.abstractThis thesis further presents a set of design techniques that can minimize the read latency of NVM-based block devices with built-in transparent compression. Leveraging the operational characteristics of error correction code (ECC) and data decompression, this thesis develops a technique that can eliminate decompression-induced read latency penalty on the read data path. It further develops a technique that can reduce the NVM physical page read latency by exploiting the fine-grained NVM accessibility and ECC coding property. A read locality aware compaction strategy is further developed to reduce block device read latency by taking advantage of abundant read locality in real-world applications. An intra-page delta encoding scheme is developed to exploit data overwrite content similarity in block devices with built-in compression. To quantitatively evaluate the developed design techniques, a NVM-based block device simulator is implemented, based upon which extensive simulations are carried out. Results show that, by deploying the developed design techniques, one not only can reduce bit cost but also can achieve much lower read latency, compared with block devices without built-in compression.
dc.description.abstractFinally, this thesis presents a simple design approach that can be easily integrated into existing mature log-structured key-value (KV) stores (e.g., RocksDB) to mitigate the impact of background compaction. Reducing compaction-induced performance degradation has been widely studied, and most prior work focused on developing innovative data structures and algorithms to directly reduce the compaction-induced write amplification.
dc.description.abstractNevertheless, it is non-trivial or even practically infeasible for existing mature KV stores to adopt these new data structures and algorithms. Meanwhile, in the presence of well-established ecosystem and community around existing ones, it is a challenge to build and grow a new log-structured KV store with meaningful real-world adoption.
dc.language.isoENG
dc.publisherRensselaer Polytechnic Institute, Troy, NY
dc.relation.ispartofRensselaer Theses and Dissertations Online Collection
dc.subjectComputer Systems engineering
dc.titleSystem architecture design for high performance solid-state data storage devices
dc.typeElectronic thesis
dc.typeThesis
dc.digitool.pid180400
dc.digitool.pid180403
dc.digitool.pid180401
dc.rights.holderThis electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
dc.description.degreePhD
dc.relation.departmentDept. of Electrical, Computer, and Systems Engineering


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