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dc.rights.licenseUsers may download and share copies with attribution in accordance with a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License. No commercial use or derivatives are permitted without the explicit approval of the author.
dc.contributorMcDonald, John F. (John Francis), 1942-
dc.contributorZhang, Tong
dc.contributorHella, Mona Mostafa
dc.contributorWashington, Morris A.
dc.contributorKraft, Russell P.
dc.contributor.authorEnglish, Kurt
dc.date.accessioned2021-11-03T09:23:19Z
dc.date.available2021-11-03T09:23:19Z
dc.date.created2021-07-07T15:42:17Z
dc.date.issued2020-12
dc.identifier.urihttps://hdl.handle.net/20.500.13015/2652
dc.descriptionDecember 2020
dc.descriptionSchool of Engineering
dc.description.abstractIn this work circuits will be presented from an initial state where operating margins were optimized to the best of the ability of a more traditional, 1-Dimentional optimization algorithm. Issues with these designs will be discussed, and improvement by the novel algorithm will be exhibited. Internal function of the optimizer to reach these improved results will be thoroughly discussed. It will be demonstrated that the resultant cell library meets all requirements for an automated placement and routing methodology using the Cadence TCAD toolset.
dc.description.abstractIn this work superconducting Single Flux Quanta (SFQ) logic cells and interconnect methodology have been developed which are compatible with Cadence design tools for automated placement and routing. SFQ logic is a digital logic using Josephson Junctions (JJs) where logic 1 is represented by the presence of a pulse, and logic 0 by the lack of a pulse.
dc.description.abstractWide process variation, thermal noise, and complexity of calculating inductances of complex structures require that SFQ circuits be built with large allowed tolerances for component values as fabricated to vary from designed values, or else circuits will be prone to error, exhibit low yield, and potentially not function at all. In the SFQ industry this acceptable variation in device parameters is known as device operating margins.
dc.description.abstractA novel automated highly parallel optimization program was developed that targets simulations on circuit problem areas, resulting in greatly improved operating margins. Automated optimization of circuits containing over 20 Josephson junctions was performed, while existing tools are limited to 5-10 junctions without user assistance. Optimization of larger circuits allows for improved margins with more compact and power efficient logic, opposed to breaking down a circuit and optimizing in pieces as required with existing tools.
dc.description.abstractUsing this algorithm a cell library was developed for automatically placed and routed designs. This cell library was previously optimized with an optimizer using a traditional linear algorithm, which demonstrated inability to adequately optimize larger circuits, and produced unsatisfactory results with a physically tested bit error rate of 1/145M at best, and as low as 1/80. Error prone outputs had simulated operating margins as low as 15%, but errors were not observed on outputs where margins were 20% or higher. The new optimizer produced circuits with all margins 33% or higher, over twice what was obtainable by a traditional optimizer and full circuit functionality with no errors is expected.
dc.language.isoENG
dc.publisherRensselaer Polytechnic Institute, Troy, NY
dc.relation.ispartofRensselaer Theses and Dissertations Online Collection
dc.subjectComputer and systems engineering
dc.titleA highly parallel automated SFQ circuit design and margin optimization tool applied to a dual rail logic single flux quanta cell library
dc.typeElectronic thesis
dc.typeThesis
dc.digitool.pid180451
dc.digitool.pid180452
dc.digitool.pid180454
dc.digitool.pid180453
dc.rights.holderThis electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
dc.description.degreePhD
dc.relation.departmentDept. of Electrical, Computer, and Systems Engineering


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