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dc.rights.licenseCC BY-NC-ND. Users may download and share copies with attribution in accordance with a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License. No commercial use or derivatives are permitted without the explicit approval of the author.
dc.contributorZhang, Tong
dc.contributor.authorSumberac, Peter
dc.date.accessioned2021-11-03T10:15:56Z
dc.date.available2021-11-03T10:15:56Z
dc.date.created2011-10-14T12:53:24Z
dc.date.issued2011-08
dc.identifier.urihttps://hdl.handle.net/20.500.13015/3387
dc.descriptionAugust 2011
dc.descriptionSchool of Engineering
dc.language.isoENG
dc.publisherRensselaer Polytechnic Institute, Troy, NY
dc.relation.ispartofRensselaer Theses and Dissertations Online Collection
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 United States*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/us/*
dc.subjectElectrical engineering
dc.titleA split instruction/data implementation of a STT MRAM last-level on-chip microprocessor cache
dc.typeElectronic thesis
dc.typeThesis
dc.digitool.pid31316
dc.digitool.pid31318
dc.digitool.pid31320
dc.digitool.pid31319
dc.digitool.pid31321
dc.rights.holderThis electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
dc.description.degreeMS
dc.relation.departmentDept. of Electrical, Computer, and Systems Engineering


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CC BY-NC-ND. Users may download and share copies with attribution in accordance with a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License. No commercial use or derivatives are permitted without the explicit approval of the author.
Except where otherwise noted, this item's license is described as CC BY-NC-ND. Users may download and share copies with attribution in accordance with a Creative Commons Attribution-Noncommercial-No Derivative Works 3.0 License. No commercial use or derivatives are permitted without the explicit approval of the author.