High speed on-chip interconnect modeling and reliability assessment

dc.rights.license	Restricted to current Rensselaer faculty, staff and students. Access inquiries may be directed to the Rensselaer Research Libraries.
dc.contributor	McDonald, John F. (John Francis), 1942-
dc.contributor	Le Coz, Yannick L.
dc.contributor	Zhang, Tong
dc.contributor	Lu, T.-M. (Toh-Ming), 1943-
dc.contributor.author	Diao, Jiedong
dc.date.accessioned	2021-11-03T10:41:01Z
dc.date.available	2021-11-03T10:41:01Z
dc.date.created	2007-05-29T13:00:48Z
dc.date.issued	2006-12
dc.identifier.uri	https://hdl.handle.net/20.500.13015/3759
dc.description	December 2006
dc.description	School of Engineering
dc.language.iso	ENG
dc.publisher	Rensselaer Polytechnic Institute, Troy, NY
dc.relation.ispartof	Rensselaer Theses and Dissertations Online Collection
dc.subject	computer
dc.subject	Systems engineering
dc.subject	Electrical
dc.title	High speed on-chip interconnect modeling and reliability assessment
dc.type	Electronic thesis
dc.type	Thesis
dc.digitool.pid	5709
dc.digitool.pid	5710
dc.digitool.pid	5712
dc.digitool.pid	5711
dc.digitool.pid	5713
dc.rights.holder	This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
dc.description.degree	PhD
dc.relation.department	Dept. of Electrical, Computer, and Systems Engineering

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Rensselaer theses from 2006; many restricted to current RPI Students, Faculty and Staff