Modeling and improving Single-Event burnout performance from heavy ion bombardment in high-voltage 4H-SiC power devices

Abstract

Silicon carbide (SiC) is a wide bandgap semiconductor recently used for developing high-voltage devices for power electronics applications on Earth and in outer space. Radiation is a serious concern for applications in the upper atmosphere and space since it can lead to Single-Event Effects (SEEs) such as permanent performance degradation, or the catastrophic device failure known as Single-Event Burnout (SEB). Despite that, SiC power semiconductor devices were expected to have improved radiation tolerance over silicon (Si) counterparts owing to its three times larger bandgap and higher operation temperature limits. Experimental studies demonstrate that SiC power devices fail at less than 50 percent of their rated blocking voltage when exposed to a single heavy ion strike and the results are similar to Si MOSFETs but lower than Si diodes. This thesis explores the physics behind failure of SiC power devices subjected to heavy ion bombardment and structural improvements to enhance SiC power device SEB performance. Physically realistic simulations are needed to understand the physics more fully and accurately capture the electro-thermal response inside a power device during and after a heavy ion strike. A high-fidelity Monte-Carlo radiation transport code was deployed to model the heavy ion strike and the corresponding generation of electron-hole pairs. Additionally, the electro-thermal effects from the ion strike were simulated using a full 3-D time-dependent electro-thermal device simulator. A toolkit was developed, enabling the radiation data generated from the Monte-Carlo simulation to be utilized by the electro-thermal device simulator, thus linking the two simulation components. The power devices investigated include the JBS diode and the MOSFET. These devices were selected for both their ubiquitousness and criticality in many power circuits. We have calibrated and validated our models against experimental studies. The failure observed in our commercial JBS and MOSFET device simulations from a heavy ion strike resulted from the generated electron-hole pairs enhancing the electric field at the epitaxial and substrate layer interface. The electric field at this interface exceeds 3 MV/cm and generates additional carriers through impact ionization. These carriers cause highly localized heating of the crystalline lattice through Joule heating. Eventually, a mesoplasma forms and the lattice temperature exceeds 3000 K, the sublimation temperature of SiC. The simulated SEB threshold voltage for these devices is 525 and 650 V for the MOSFET and JBS diode, respectively. Traditionally the ratio of the SEB threshold voltage and breakdown voltage (SEB/BV) is the figure of merit (FoM) used to evaluate how robust a design is against a heavy ion strike. A ratio of 1 means that the design is immune to SEB. The simulated MOSFET and JBS diode have a SEB/BV ratio of 0.30 and 0.38, respectively. We developed new FoMs which consider both the on-state and SEB performance for the MOSFET and JBS diode. The values obtained using these FoMs are 0.12 and 0.29 for the simulated MOSFET and JBS diode, respectively. Several designs to improve SEB performance by suppressing the electric field enhancement at the epitaxial and substrate interface were proposed and confirmed with simulations. Using these designs, the SEB threshold voltage was increased between 46 and 81 percent and the on-performance tradeoff was between 1 to 53 percent over the baseline commercial designs. These designs also increases the SEB/BV ratio by at least a factor of 1.26 over the baseline designs and our new FoM by at least a factor of 1.27. We propose several device structures using these designs to create 1200 V SEB rated power devices for both the JBS diode and MOSFET. We also evaluated the SEB performance of Superjunction (SJ) planar MOSFETs, which have a superior specific on-resistance over conventional designs but experience an SEB/BV ratio that is 46 percent lower compared to conventional non-SJ MOSFETs of similar drift layer thickness. However, employing our new FoM, the SJ MOSFET outperforms the commercial design by a factor of 7. Further SEB performance improvement can be realized by employing a Semi-SJ design, which results in a SEB/BV ratio that is 89 percent higher, the specific on-resistance increases less than 5 percent, and the FoM is 74 percent higher compared to the SJ MOSFET.