Comparative performance evaluation of conventional and superjunction vertical 4H-silicon carbide high-voltage power mosfets
Authors
Torky, Mohamed
ORCID
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Other Contributors
Dutta, Partha S.
Sun, Jian
Ji, Wei
Chow, T. Paul
Sun, Jian
Ji, Wei
Chow, T. Paul
Issue Date
2022-05
Keywords
Electrical engineering
Degree
MS
Terms of Use
Attribution-NonCommercial-NoDerivs 3.0 United States
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute (RPI), Troy, NY. Copyright of original work retained by author.
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute (RPI), Troy, NY. Copyright of original work retained by author.
Full Citation
Abstract
4H-SiC exhibits a 10× higher critical breakdown field than silicon, enabling its high-voltage power devices possible to achieve >1000x smaller specific on-resistance (RON,sp) than Si-based devices at the same breakdown voltage (BV). In addition, high-voltage superjunction (SJ) devices have better performance than conventional devices due to a lower drift specific on-resistance, reducing the conduction power loss. In this thesis, we comparatively evaluate 0.6-10kV-rated, vertical power DMOS and UMOS FETs with their SJ counterparts, in 4H-SiC, in terms of their static and dynamic switching performances.
The static conduction loss of these transistors is estimated from the specific on-resistance, which is calculated using analytical expressions for each region. We utilize the specific total charge QT,sp for the dynamic switching power loss, extracted from TCAD (Sentaurus) simulations. Also, the turn-on time (ton), turn-off time (toff), and switching energy loss per cycle (Esw/cycle) are determined.
The specific on-resistance is reduced by 89 and 78% for SJ UMOS and DMOS, respectively, compared to their conventional counterparts at 3.3kV due to higher pillar doping and lower drift layer resistance. The QT,sp reduction is reduced by 8 and 20% at all BV ratings. The lower RON,sp of UMOS devices is due to a higher channel density than DMOS devices, hence better RCH,sp. The turn-off time is higher for UMOS FETs because of higher QT,sp, hence, higher switching energy losses per cycle.
Moreover, the SJ UMOS FET with the narrowest pillar width exhibits substantial reduction (up to 24, and 99 %) in our NFOM (RON,sp . QT,sp) compared to conventional UMOS FET at 0.6 to 10kV respectively because drift layer resistance dominates at high BV ratings. Meanwhile, the reduction is 30%, 30%, and 81% in SJ DMOS at the same breakdown voltage ratings. SJ UMOS has a higher switching losses due to a 67% higher QT,sp compared to SJ DMOS, but it has a significant lower 47% in RON,sp, achieving the lowest FOM, with a reduction of 53 to at least 31% compared to SJ DMOS FET at the same BV ratings respectively because the specific on-resistance of both devices approaches the same value at high BV ratings.
In summary, the SJ UMOS FET has the best performance in terms of the lowest FOM among the SJ and conventional power MOSFETs compared, inferring to have the lowest total (conduction and switching) energy loss.
Description
May 2022
School of Engineering
School of Engineering
Department
Dept. of Electrical, Computer, and Systems Engineering
Publisher
Rensselaer Polytechnic Institute, Troy, NY
Relationships
Rensselaer Theses and Dissertations Online Collection
Access
CC BY-NC-ND. Users may download and share copies with attribution in accordance with a Creative Commons
Attribution-Noncommercial-No Derivative Works 3.0 license. No commercial use or derivatives
are permitted without the explicit approval of the author.