Show simple item record

dc.rights.licenseRestricted to current Rensselaer faculty, staff and students. Access inquiries may be directed to the Rensselaer Libraries.
dc.contributorLu, James
dc.contributorDutta, Partha S.
dc.contributorPersans, Peter D., 1953-
dc.contributorZhang, Tong
dc.contributor.authorZhang, Dingyou
dc.date.accessioned2021-11-03T07:59:38Z
dc.date.available2021-11-03T07:59:38Z
dc.date.created2013-09-09T14:53:57Z
dc.date.issued2013-05
dc.identifier.urihttps://hdl.handle.net/20.500.13015/888
dc.descriptionMay 2013
dc.descriptionSchool of Engineering
dc.description.abstractA novel chip-to-wafer 3D integration approach that requires only one thermal cycle is developed, demonstrated and evaluated. Among the three major 3D approaches, the C2W approach, taking the advantages of both the C2C and W2W approaches, is able to achieve high yield using known-good-dies (KGDs) and improve the throughput using wafer-level processes. In addition, it allows effective stacking chips with different sizes in wafer level. However, the sequential alignment and bonding of top chips to a host wafer associated with the existing C2W 3D approaches result in lower throughput and require a thermal cycle for each chip bonding. Moreover, the C2W alignment and bonding by pick-and-place tools has to be in atmosphere, which limits the alignment accuracy and constrains the bonding materials and methods. To address these challenges, the novel C2W 3D integration approach developed in this work uses a template alignment and well-controlled wafer-level bonding. With the template as positioning reference, precise alignment accuracy has been achieved, while the C2W alignment process is independent of commercial alignment tools. Simultaneous bonding of all the top chips to a host wafer under well-controlled conditions is demonstrated, leading to high throughput and few thermal cycles. Short-loop experiment further validates the feasibility of this approach. Key fabrication processes are evaluated, including chip and wafer fabrication, chip edge definition, template fabrication, C2W alignment and wafer- level bonding, electrical characterization and thermal reliability test.
dc.description.abstractThis novel C2W 3D technology developed, which can reduce the potential thermo- mechanical failures (including TSV protrusion), can enable the high throughput fabrication for developing future 3D integrated systems.
dc.description.abstractThermally-induced copper TSV length increase, known as "TSV protrusion", can cause mechanical and electrical failures. This work systematically evaluates the TSV thermo-mechanical reliability based on wide range thermal shock and thermal cycling tests. A new TSV failure is discovered, i.e., TSV backside protrusion after thermal treatments at temperature above 250 °C. Metrologies to quantify TSV protrusion are developed and employed to study the effects of various accelerating factors on TSV protrusions, including peak temperature and ramp up/down rate. The average TSV protrusion increases from ~0.1 μm at 250 °C to ~0.5 μm at 400 °C, and can be fitted to an exponential function with an activation energy of ~0.6 eV, suggesting a Cu grain boundary diffusion mechanism. Microstructure analysis of TSV-based 3D structures reveals various failures that may cause TSV protrusion and potential reliability issues with thermal cycling at high temperatures (i.e., above 250 °C). Thus, it is critical to reduce high temperature thermal cycles for TSV-based 3D integration realization.
dc.description.abstractThree-dimensional (3D) integration, which can stack different materials, technologies and functional components vertically, is a promising technology to overcome some physical, technological, and economic limits encountered in planar ICs, extending Moore's Law and enabling "More than Moore" applications. Three major approaches have been explored to realize 3D integration: chip-to-chip (C2C), chip-to-wafer (C2W) and wafer-to-wafer (W2W). A key enabling component in most 3D integration technologies is the through-silicon via (TSV). Based on the advances on 3D TSV technologies, this thesis work examines TSV thermo-mechanical reliability issues and develops a novel C2W 3D integration approach.
dc.language.isoENG
dc.publisherRensselaer Polytechnic Institute, Troy, NY
dc.relation.ispartofRensselaer Theses and Dissertations Online Collection
dc.subjectElectrical engineering
dc.titleA novel chip-to-wafer 3D integration technology
dc.typeElectronic thesis
dc.typeThesis
dc.digitool.pid167169
dc.digitool.pid167170
dc.digitool.pid167171
dc.rights.holderThis electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
dc.description.degreePhD
dc.relation.departmentDept. of Electrical, Computer, and Systems Engineering


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record