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dc.rights.licenseRestricted to current Rensselaer faculty, staff and students. Access inquiries may be directed to the Rensselaer Libraries.
dc.contributorLu, James Jian-Qiang
dc.contributorRose, K. (Kenneth)
dc.contributorZhang, Tong
dc.contributorLe Coz, Yannick L.
dc.contributorCarothers, Christopher D.
dc.contributor.authorBeece, Adam Patrick
dc.date.accessioned2021-11-03T07:59:45Z
dc.date.available2021-11-03T07:59:45Z
dc.date.created2013-09-09T14:55:05Z
dc.date.issued2013-05
dc.identifier.urihttps://hdl.handle.net/20.500.13015/895
dc.descriptionMay 2013
dc.descriptionSchool of Engineering
dc.description.abstractThe overall conclusion is that footprint, capacity and power will be the main drivers for the adoption of 3D integration in the near future.
dc.description.abstractA new simulator, called RGS, is presented for estimating the performance of GPUs. This simulator is validated against some highly optimized matrix multiplication benchmarks, and shows very good agreement. However, on general-purpose GPU systems, there are minimal performance gains from 3D integrated memory (again in the range of a few percent). There is definite power savings, at least 3-6 W on a board with a worst case power consumption of <225 W. Unlike with CPU benchmarks, GPUs showed the best results not with bringing memory closer, but with elimination of off-chip accesses by integrating large memory directly onto the chip.
dc.description.abstractWith an ideal memory, an upper bound on performance improvement is observed to be approximately 50% for single-threaded applications or 137% for multi-threaded applications. The observed performance gains with realistic memory are less than 2%, suggesting that performance is not a significant driver for 3D integration (at least not for the benchmark applications). System level power savings are projected to be in the range of 10 % of total server power based on eliminations of off-chip I/O parasitics alone. Performance and power are most improved by bringing the DDR3 DRAM closer to the processor (replacing DDR3 with silicon-on-interposer and true 3D stacking).
dc.description.abstractFull system CPU simulator M5 is selected to evaluate the effects of 3D integrated memory on servers running academic applications in terms of power and performance. Simulation was limited to a collection of SPEC 2000 and 2006 benchmarks that are not memory capacity limited. Due to limitations in either the tool or the build environment, further use of M5 for this purpose cannot be recommended.
dc.description.abstractTo model TSVs swiftly in a design space exploration sense, a simple RC model of a TSV is constructed, and validated to the high fidelity full wave electromagnetic simulation. This RC model is compared to both an RLC circuit model and the approach of completely ignoring the parasitics inherent in the TSV. There is little accuracy improvement by including inductive effects for our sample via. However, ignoring the effect of TSVs on a memory array can artificially decrease the predicted circuit latency by as much as 5% in even a 2-tier 3D stack, with the misprediction growing with the number of tiers.
dc.description.abstractThree-dimensional (3D) integration is an emerging disruptive technology that offers significant potential advantages, especially in terms of memory/processor interaction. It can offer dramatic increases in the accessibility of memory; however, such changes do not always translate into commensurate improvements in performance, e.g., the execution time for a given task.
dc.description.abstractThe CACTI memory array simulator is augmented with the TSVs to arrive at predictions of how 3D stacked memory arrays (SRAM and DRAM) compare in terms of power and performance to designs. Footprint and latency are decreased, while power savings are minimal.
dc.description.abstractSignificant research has been done on how 3D integration may improve certain subsystems, and on how it might be implemented, but there is a lack of comprehensive studies that espouse both a solid understanding of the circuit-level impact of the technology and a full-system level understanding of its impact. This work covers these two extremes, from modeling through-strata vias (TSVs) at the circuit level of individual transistors and parasitic wire resistance to modeling at the circuit level, and to counting hundreds of millions of instructions at the system level. In particular, this work examines the potential benefits of 3D memory and its interactions with CPU and GPU - two major types of performance-driven processing units.
dc.language.isoENG
dc.publisherRensselaer Polytechnic Institute, Troy, NY
dc.subjectElectrical engineering
dc.titleImproving computer system performance and power with 3D integration of memory
dc.typeElectronic thesis
dc.typeThesis
dc.digitool.pid167188
dc.digitool.pid167191
dc.digitool.pid167192
dc.rights.holderThis electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
dc.description.degreePhD
dc.relation.departmentDept. of Electrical, Computer, and Systems Engineering


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