Circuits and systems for solid-state data storage using highly scaled NAND flash memory

Authors
Zhao, Kai
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Other Contributors
Zhang, Tong
Hella, Mona Mostafa
Saulnier, Gary J.
Carothers, Christopher D.
Issue Date
2014-12
Keywords
Electrical engineering
Degree
PhD
Terms of Use
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
Full Citation
Abstract
Solid-state data storage built upon NAND flash memory is fundamentally changing the memory and storage hierarchy for virtually the entire information technology infrastructure. This grand industrial trend is essentially driven by the steady bit-cost reduction of flash memory, which is enabled by continuous semiconductor technology scaling. Unfortunately, technology scaling makes flash memory devices subject to increasingly severe noise and distortion, which can largely degrade NAND flash memory storage reliability and performance. Error correction code (ECC) plays a critical role in ensuring overall system data storage integrity in presence of flash memory device reliability degradation. Conventional ECCs, such as the widely used Bose-Chaudhuri-Hocquenghem (BCH) code, have become increasingly inadequate as technology continues to scale down. Therefore, it is highly desirable to deploy a much more powerful ECC, such as low-density parity-check (LDPC) code. This thesis investigates the key design issues in practical application of LDPC code in flash-based solid-state drive (SSD).
Description
December 2014
School of Engineering
Department
Dept. of Electrical, Computer, and Systems Engineering
Publisher
Rensselaer Polytechnic Institute, Troy, NY
Relationships
Rensselaer Theses and Dissertations Online Collection
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