Enabling extreme-scale circuit modeling using massively parallel discrete-event simulations

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Gonsiorowski, Elsa
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Electronic thesis
Computer science
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Simulation is a key step in designing complex integrated circuits, such as processors. In recent years, chip complexity has increased to the point that sequential simulation tools are no longer adequate. Many commercial gate-level simulation tools are limited in scale or require specialized hardware approaches, thus limiting effective software simulation to sub-components of the larger circuit. Parallel discrete-event simulation (PDES) is a perfect fit for this context. The key contribution of this thesis is a complete software- based workflow for transforming domain-specific designs into an accurate PDES model that is able to execute and leverage the compute capabilities of modern supercomputer systems.
Finally, I describe an efficient parallel I/O API, called RIO, designed specifically for PDES applications. RIO enables a parallel, checkpoint-restart capability for long- running, parallel simulations. These checkpoints are compact and are written in binary format. For efficient parallel I/O operations, the metadata are stored in separate files from the pieces of simulation object data. To ensure data preservation and legacy, a human- readable description file accompanies each set of checkpoint data files.
Next, I present a circuit model mapping workflow. It is through this mapping that I am able to take a multi-component description of a full-scale circuit and instantiate it within ROSS. Each components original listings of logic gates connected to named wires becomes a listing of simulation objects with internal knowledge of their connections to other simulation objects. The final step is the instantiation of the components and including the high-level routing between modules.
I begin by presenting an automatic model generation tool which accurately trans- forms a gate library description from a domain-specific grammar to C. Through the ex- emplar LSI-10K library, this tool is able to capture both logic and timing information for each of the 166 gate types. This C-based expression of the library is combined with a novel, generic gate model for Rensselaer’s Optimistic Simulation System (ROSS).
Circuit designs at the logic level are built upon a gate library. This library describes the physical properties of the logic components for the circuit (e.g., boolean logic gates). By using a relatively small set of logic gates, the larger circuit design, such as an entire processor, is realized.
May 2016
School of Science
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Rensselaer Polytechnic Institute, Troy, NY
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