Low-power time-to-digital converters for high-precision measurement

Thumbnail Image
Tong, Xing
Issue Date
Electronic thesis
Electrical engineering
Research Projects
Organizational Units
Journal Issue
Alternative Title
Time-to-digital converters (TDCs), which converts time delays into digital signals, have garnered significant interest for their diverse applications in fields such as high-energy nuclear physics, time-of-flight (ToF) sensors, time-domain analog-to-digital converters (TD-ADCs), and all-digital phase-locked loops (ADPLLs). The performance of a TDC is primarily measured by its resolution, range, sampling rate, and power consumption. To simultaneously achieve a fine resolution and a long range, or a high dynamic range, in an area and power efficient manner, hierarchical architectures with the potential to combine the advantages of several different approaches has been studied. This thesis investigated three different hierarchical designs implemented in technologies ranging from 350nm CMOS to 45nm SOI, each suitable for its specific applications. This work first presents a hierarchical ADC-assisted TDC with reconfigurable resolution. The reconfigurable resolution and range are achieved by adjusting reference currents in the time-to-voltage converter (TVC) and the reference voltages in the ADC. The proposed resolution-reconfigurable approach combined with a two-step hierarchical architecture can be employed in a wide range of applications with different spatial range and resolution requirements. Fabricated using a 350nm CMOS process with a core area of 0.15mm², prototype chips yielded a resolution of 39ps with a 100MHz reference clock or 78ps with a 50MHz reference clock. In both cases, the measurement rate is 384kS/s while consuming less than 6.7mW from a 3.3V supply. Secondly, a multi-channel 4-tier TDC design combining gated-ring oscillators (GRO) coarse measurement stage, time amplifier, and 2D vernier fine measurement stage designed an simulated in 90nm SOI SiPh process. A dual-counter correction scheme is proposed to address the parallel-output-misalignment (POM) error in multi-phase clock based TDCs. The finer two tiers employ time amplifiers and 2D vernier lines to measure the residual signal, achieving a sub-gate-delay resolution while keeping a high conversion rate. Post-layout extracted simulation on the proposed TDC design shows a 2ps LSB size, while consuming 5.11-mW per additional channel from a 1.2V supply when operating at the maximum sampling rate of 500MS/s. Compared to state-of-the-art TDC designs, the proposed architecture shows an improvement in quantization step, conversion time, and dynamic range. The idea of multiphase-clock-based multichannel coarse measurement is further explored in a DLL-based TDC implemented in 45nm SOI technology. Lastly, a hierarchical pipeline TDC in 45nm SOI technology, optimized for high-speed and high-precision applications, is introduced. A novel analytical model for the cross-coupled time amplifier (TA) in the pipeline TDC is formulated. Based on this model, a gain calibration scheme is proposed. To validate the time amplifier analysis, a hierarchical TDC with pipeline fine measurement is designed and fabricated in 45nm SOI technology. With look-up table correction, measurement results of the TDC demonstrate a resolution of 0.95ps, a range of 0.8ns, and a DNL/INL range of 2.14 LSB and 2.13 LSB, respectively. The device operates on 8.851mW from a 1.0V supply at a sampling rate of 120MHz, and it achieves a maximum sampling rate of at least 250MHz, highlighting its capability to simultaneously deliver high speed and fine resolution.
School of Engineering
Full Citation
Rensselaer Polytechnic Institute, Troy, NY
Terms of Use
PubMed ID