A novel chip-to-wafer 3D integration technology
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Authors
Zhang, Dingyou
Issue Date
2013-05
Type
Electronic thesis
Thesis
Thesis
Language
ENG
Keywords
Electrical engineering
Alternative Title
Abstract
A novel chip-to-wafer 3D integration approach that requires only one thermal cycle is developed, demonstrated and evaluated. Among the three major 3D approaches, the C2W approach, taking the advantages of both the C2C and W2W approaches, is able to achieve high yield using known-good-dies (KGDs) and improve the throughput using wafer-level processes. In addition, it allows effective stacking chips with different sizes in wafer level. However, the sequential alignment and bonding of top chips to a host wafer associated with the existing C2W 3D approaches result in lower throughput and require a thermal cycle for each chip bonding. Moreover, the C2W alignment and bonding by pick-and-place tools has to be in atmosphere, which limits the alignment accuracy and constrains the bonding materials and methods. To address these challenges, the novel C2W 3D integration approach developed in this work uses a template alignment and well-controlled wafer-level bonding. With the template as positioning reference, precise alignment accuracy has been achieved, while the C2W alignment process is independent of commercial alignment tools. Simultaneous bonding of all the top chips to a host wafer under well-controlled conditions is demonstrated, leading to high throughput and few thermal cycles. Short-loop experiment further validates the feasibility of this approach. Key fabrication processes are evaluated, including chip and wafer fabrication, chip edge definition, template fabrication, C2W alignment and wafer- level bonding, electrical characterization and thermal reliability test.
Description
May 2013
School of Engineering
School of Engineering
Full Citation
Publisher
Rensselaer Polytechnic Institute, Troy, NY