A split instruction/data implementation of a STT MRAM last-level on-chip microprocessor cache
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Authors
Sumberac, Peter
Issue Date
2011-08
Type
Electronic thesis
Thesis
Thesis
Language
ENG
Keywords
Electrical engineering
Alternative Title
Abstract
Description
August 2011
School of Engineering
School of Engineering
Full Citation
Publisher
Rensselaer Polytechnic Institute, Troy, NY