Studies of the interfacial layer in high-k/metal gate transistors

Authors
Jamison, Paul C.
ORCID
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Other Contributors
Gall, Daniel
Shi, Jian
Ramanath, G. (Ganpati)
Issue Date
2016-08
Keywords
Materials science and engineering
Degree
MS
Terms of Use
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
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Abstract
HfO2 layers, 25-Å-thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yields a high- gate stack for which the original 8-Å-thick SiO2 layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate stack achieve an equivalent oxide thickness in inversion Tinv = 9.7 Å, with a gate leakage Jg = 0.8 A/cm2. Devices fabricated without in-situ annealing of the HfO2 layer yield a Tinv which increases from 10.8 to 11.2 Å as the oxidation time during each HfO2 growth cycle increases from 10 to 120 s, also causing a decrease in Jg from 0.95 to 0.60 A/cm2, and an increase in the transistor threshold voltage from 272 to 294 mV. The in-situ annealed devices have a 1.5 Å (`10%) lower Tinv but 0.1 A/cm2 (~30%) higher gate leakage, as well as a 60 mV reduction in Vt . These positive effects are attributed mainly to the oxygen-deficiency of the as-deposited HfO2, which facilitates both the reduction of an interfacial SiO2 layer as well as a partial phase transition to a high- cubic or tetragonal HfO2 phase.
Description
August 2016
School of Engineering
Department
Dept. of Materials Science and Engineering
Publisher
Rensselaer Polytechnic Institute, Troy, NY
Relationships
Rensselaer Theses and Dissertations Online Collection
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