Wideband phase locked loop (pll) for sub-mmwave applications
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Authors
Saquib, Nazmus
Issue Date
2024-08
Type
Electronic thesis
Thesis
Thesis
Language
en_US
Keywords
Electrical engineering
Alternative Title
Abstract
Frequency generation is pivotal for the implementation of high-frequency electronic systems. Such circuits must deliver signals with precise frequency locations. The signal source mustalso be tunable over a wide bandwidth. Phase Locked Loops (PLLs) ensure this precision by providing feedback. PLLs are evaluated based on their phase noise, tuning range, output power, and
overall DC power consumption. For communication applications, low phase noise is critical due
to its impact on signal integrity, frequency stability, and interference mitigation. Enhancing the
signal-to-noise ratio (SNR) of communication transceivers necessitates high output power from
the local oscillator (LO) to drive mixers into saturation, thereby reducing conversion loss or increasing conversion gain. In sub-mmWave/THz applications, the PLL must offer a broad tuning
range to exploit the available bandwidth.
This research focuses on the design, implementation, and testing of PLLs operating above
100 GHz using Fully Depleted Silicon on Insulator (FDSOI) technology, targeting future 6G applications in the D-band. These PLLs, when coupled with frequency multipliers, extend into the
THz frequency bands, facilitating applications in THz wave sensing and spectroscopy. GlobalFoundries’ 22nm fully depleted silicon on insulator (FDSOI) technology is utilized, offering ultralow power DC consumption and a compact form factor. The technology features thin oxide devices
with nominal core voltages as low as 0.4V and provides forward/reverse back gate bias options for
threshold voltage control. Additionally, the transistors support different gate pitches and have
multiple metal layers to meet electro-migration rules, ensuring reliable long-term operation. This
technology’s stack includes ten metal layers, with two thick copper layers and a 2.8µm top aluminum layer, providing high performance for mmWave designs.
The thesis objective is to design sub-mmWave PLLs that balance wide tuning range, low
phase noise, and relatively high output power while minimizing energy consumption. This challenge is heightened by the limitations of standard silicon technology with low-quality passives at such high frequencies. Research on PLLs above 100 GHz is still in its early stages due to the
complexities of designing efficient and robust integrated circuits (ICs) at these frequencies, compounded by device limitations, process variations, and imprecise measurements and device models.
Traditional PLL architectures, involving a voltage-controlled oscillator (VCO), frequency divider,
phase/frequency detectors, charge pump, and loop filter, must be reconsidered for D-band and
higher frequencies due to the limited tuning range of sub-mmWave VCOs and the high power consumption of high-frequency dividers. Therefore, a harmonic PLL is designed that utilizes a dual
resonant VCO that generate both 1st and 3rd harmonic signals. Furthermore, a W-band Fundamental PLL is proposed that utilizes a magnetically tuned VCO along with Dynamic latch divider.
Both designs are fabricated in 22nm FDSOI technology and tested to validate the performance
metrics. The fundamental dual band PLL achieves frequency range of 87 GHz to 104 GHz, delivering a peak output power of -7 dBm while consuming 53.1 mW of DC power. Key components,
including the varactorless VCO, a dynamic latch frequency divider, and an implicit reset phasefrequency detector, collectively ensure minimal phase noise at -105 dBc/Hz at a 10 MHz offset and
an integrated RMS jitter between 108 and 110 fs. Finally a comparison between two architectures
of PLL is presented to summarize performance metrics for the research community.
Description
August 2024
School of Engineering
School of Engineering
Full Citation
Publisher
Rensselaer Polytechnic Institute, Troy, NY