High speed capacitance extraction in integrated circuits using a stochastic random-walk algorithm

Authors
Sharma, Aditya S.
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Other Contributors
Le Coz, Yannick L.
Issue Date
1991-05
Keywords
Computer Systems engineering
Degree
MS
Terms of Use
This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute, Troy, NY. Copyright of original work retained by author.
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Abstract
This thesis presents the basic development and subsequent application of a novel stochastic algorithm for high-speed capacitance extraction in complex integrated circuits. The algorithm is an optimized variant of the Floating Random-Walk Method. Its overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical error cancellation, selective integration over electrode Guassian surfaces and direct capacitance-matrix evaluation. Computational experiments were carried out to demonstrate the improvement in execution time and accuracy in calculating capacitance in complex integrated circuits. The underlying premise of this thesis is to show that stochastic techniques are viable alternatives to deterministic techniques for high speed capacitance extraction in integrated circuits, especially as we move towards Ultra Large Scale Integration (ULSI) and Giga Scale Integration (GSI).
Description
May 1991
School of Engineering
Department
Dept. of Electrical, Computer, and Systems Engineering
Publisher
Rensselaer Polytechnic Institute, Troy, NY
Relationships
Rensselaer Theses and Dissertations Online Collection
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