Development of a methodology for automatic placement and routing of sfq circuit designs and an associated standard cell library
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Authors
Nath, Sagnik
Issue Date
2020-05
Type
Electronic thesis
Thesis
Thesis
Language
ENG
Keywords
Electrical engineering
Alternative Title
Abstract
Then, the place and route methodology is extended to HDL designs comprising memory by adding a Non Destructive Readout (NDRO) Flip Flop to the SFQ cell library. Three HDL designs were passed through this place and route methodology : a 4-bit ALU, 4-bit Register File and a 11-bit Processor operating on 4-bits of word. All three designs were successfully converted to layouts and had functionality verified through analog simulations with back annotated interconnect wire lengths. This has been discussed at length in published paper "An Automatic Placement and Routing Methodology for Asynchronous SFQ Circuit Design" (DOI:10.1109/TASC.2019.2942263)
Description
May 2020
School of Engineering
School of Engineering
Full Citation
Publisher
Rensselaer Polytechnic Institute, Troy, NY