Silicon photonic devices for neuromorphic computing and optical acceleration

Abstract

The exponential growth of artificial intelligence (AI) and data center workloads have outpaced the computation capabilities of conventional von Neumann computing architectures implemented in CMOS electronics, particularly in terms of speed and energy efficiency. Silicon photonics has emerged as a promising platform for implementing both neuromorphic computing systems and photonic accelerators for matrix–vector multiplication (MVM). This dissertation investigates active silicon photonic devices and chip-scale optical systems for two computing paradigms: photonic reservoir computing (RC) for temporal and sequential signal processing, and photonic tensor cores (PTCs) for general matrix multiplication. A key challenge in RC is the computational complexity associated with hyperparameter optimization. In this dissertation, a sinusoidal time-evolution model derived from hardware parameters is developed, and a bifurcation dynamics–guided optimization framework has been explored to significantly reduce the computational burden. This method is validated on a bench top RC system using RC benchmark tasks (NCE, NARMA10, and Santa Fe time series) as well as clinically collected respiratory tumor motion datasets, achieving comparable accuracy to conventional optimization approaches. Integrated photonic RC using silicon photonic foundry fabrication has also been explored. A two-dimensional (2D) chaotic cavity-based reservoir is implemented with a series of evanescently coupled photodetectors (PDs) positioned near the cavity boundary. Experimental results demonstrate rich spatial and spectral dynamics, although nonlinear response remains limited. Additionally, a true-time-delay (TTD) RC architecture is realized using spiral waveguides to provide nanosecond-scale delay. While photonic circuit functionality is confirmed, insertion loss and unwanted electrical reflection limit the system performance. A revised low-loss design has been submitted for fabrication to mitigate the current system-level limitations. For photonic tensor core research, this dissertation presents several novel device innovations. First, a single Bragg grating modulator (SBG-M) with an ultra-compact footprint of 10 um by 50 um has been developed, achieving a normalized mean square error (NMSE) of 0.0005 at 6-bit resolution and 20 kHz operation frequency, with an average power consumption of 5.29 mW and a stable performance up to 65°C. Second, a slow-light electro-optic Mach–Zehnder modulator (SL-MZM) enabled by Bragg grating engineering achieves a 3~10x reduction in phase shifter length, with 6-bit resolution, NMSE of 0.0018 and operation at 800 MHz with ~100 uW power consumption. Third, contra-directional coupling–based wavelength-selective couplers (WSCs) are designed and implemented in silicon and hybrid vertical Si/SiN configuration for wavelength routing and signal combining. These device innovations establish key building blocks for scalable photonic computing and optical interconnect architectures. In collaboration with other groups, a time-multiplexed dynamic photonic tensor core (PTC) architecture is explored, achieving a 6.8x system area reduction and a 9.1x system power reduction driven by the device-level innovations. Additionally, sub-wavelength grating (SWG)-assisted power couplers are investigated for complex optical interconnects on a glass interposer. Together, this dissertation advances the development of energy-efficient, high-speed photonic computing systems for next-generation AI and data center applications.