Dielectric conduction mechanisms pre- and post- intrinsic breakdown
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Authors
Xu, Yueming
Issue Date
2021-05
Type
Electronic thesis
Thesis
Thesis
Language
en_US
Keywords
Chemical engineering
Alternative Title
Abstract
Dielectric breakdown is the phenomenon where an insulator degrades and its leakage current increases significantly. A lightning strike between the cloud and ground is the most common example of a dielectric breakdown event. The time-dependent dielectric breakdown (TDDB) occurring at the interconnect level in an integrated circuit has become an increasingly serious reliability issue as devices get smaller. Numerous closed-form lifetime acceleration models have been proposed to extrapolate the lifetime measurements obtained under high temperature and high-field testing conditions to the lifetime under working conditions. A charge transport model was developed to simulate and achieve a better understanding of TDDB. The charge transport model (CT model) is a one-dimensional dynamic model, that consists of a set of non-linear partial differential equations (PDEs) which replicate electronic conduction through the dielectric. The dielectric breakdown phenomenon, however, is not necessarily a reliability issue. It has positive effects and can be exploited for device operation. Resistive random access memory (ReRAM) is one example of devices that exploit breakdown phenomena. In this study, the aforementioned CT model is modified and extended to also simulate the post-breakdown region. A linear post-breakdown region appears automatically following the abrupt change in current under a ramped voltage stress. The breakdown event has a strong correlation with percolation theory. Intrinsic dielectric breakdown is driven by defects (traps) in the material and occurs only when the local trap concentration reaches a percolation threshold. The percolation threshold is found to be 0.03 for the studied system. The completion of the percolation path indicates the first breakdown event often called the soft breakdown point. The occurrence of hard breakdown, or final failure, is attributed to the saturation in the number of intrinsically generated defects in the dielectric material. The saturation value for each dielectric system can be obtained from the fitting parameters extracted from the CT model. The industrial definition of the time-to-failure (TTF) may result in a premature breakdown especially when a high constant voltage stress is applied. The dynamic process underlying formation of the percolation path is visualized by the trap distribution evolution in the model. The percolation path always originates near the anode and terminates near the cathode, though the trap distribution evolution varies with the stressing methods. The weakest link during the percolation path formation and also the most possible location of the filament rupture during the RESET process for ReRAM devices is found to be the cathode/dielectric interface when a ramped voltage stress or a high constant voltage is applied; however, under a low constant voltage stress, the weakest link migrates from the center of the dielectric to the cathode/dielectric interface upon the formation of the conductive pathway. A relationship between the abruptness of the current increase at the failure point and the unevenness of the trap distribution when the percolation path starts forming is found, which will be verified with future plans including pre-implantation of traps near the anode or increasing the ramp rate during the forming process. A less abrupt current increase during the forming or SET process is favored by 3D crossbar structures and by multilevel cell ReRAM devices. The percolation path formation can be manually controlled by switching offthe trap generation in the CT model. A transition from an insulator region to a metallic-like region is observed based on the temperature dependence simulation results with the controlled breakdown. The post-breakdown conductance is found to be linearly dependent on the current limit, the current level when the trap generation is stopped, which agrees with the experimental results on multi-level cell ReRAM devices where the SET state conductivity has a linear relationship with the preset current compliance. To precisely describe how electrons move through the percolation path, trap-trap tunneling is proposed and these electrons are treated exactly the same as drifting in the CT model. A Superlattice model and a Nasyrov-Gritsenko (N-G) model are discussed and compared as alternative mechanisms. The Superlattice model is able to predict a linear I-V characteristic only with an unrealistic Fermi level at the cathode. The N-G model was adapted for the trap-trap tunneling current calculation with a formed percolation path by the CT model and the post-breakdown linear I-V characteristic can be realized. However, the weak temperature dependence of the post-breakdown region can be only realized when the optical excitation energy is preset really close to the trap depth from the conduction band. Future work on the temperature dependence of the post- intrinsic hard breakdown and also on the possibility and requirement for the optical excitation energy to be abnormally small may help decide whether N-G model should be adapted.
Description
May 2021
School of Engineering
School of Engineering
Full Citation
Publisher
Rensselaer Polytechnic Institute, Troy, NY