Multirate digital signal processing for time interleaved analog to digital converters

Kouada, Ibrahim, Issoufou
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Zhang, Tong
Sanderson, Arthur, C
Carothers, Christopher, D
McDonald, John, F
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Electrical engineering
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This electronic version is a licensed copy owned by Rensselaer Polytechnic Institute (RPI), Troy, NY. Copyright of original work retained by author.
Full Citation
In today’s increasingly higher speed and higher data rate world, high speed Analog to Digital Converters (ADCs) are very much in demand. They are needed in multiple applications including communications, radars, software defined radio, high speed digital oscilloscopes to cite a few. Time interleaving two or more ADCs running at a lower sampling rate enables achieving a higher sampling rate. Interleaving N sub-ADCs operating at a sampling rate Fs would ideally result in a Time Interleaved ADC (TIADC) with an N fold increased sampling rate. However, interleaving comes with a set of challenges. Offset, Gain and timing skew mismatches between the sub-ADCs cause undesired degradations in the performance of the TIADC. The purpose of this research work is to design and implement a programmable Digital Signal Processing (DSP) module that will help mitigate the offset, Gain and timing skew mismatches encountered in TIADCs. The core building block of the Digital Signal Processing module implemented in the first part of this thesis work is a fractional delay filter for detecting timing skew mismatches preceded by Offset and Gain mismatch compensation modules. Various building blocks of the Digital Signal Processing module for minimizing the effect of TIADC mismatches are implemented using the IBM CMOS 9HP standard cell library which is part of the IBM BICMOS 9HP technology kit. In the second part, a scalable, extremely efficient timing skew detection and compensation technique using a single FIR filter once, is developed; enabling close to 50% reduction in hardware resource utilization compared to current state of the art timing skew calibration techniques. This efficient timing skew calibration technique is then expanded to incorporate a current state of the art gain mismatch calibration resulting in a very efficient all digital background gain and timing skew mismatch calibration algorithm. Future work includes the integration of the Digital Signal Processing module with a 2-way TIADC designed using the Heterojunction Bipolar Transistor (HBT) devices which are part of the IBM BICMOS 9HP kit. One could also envision implementing the timing skew detection and mitigation technique developed in this research work for a 4-way, 8-way TIADC and beyond.
School of Engineering
Dept. of Electrical, Computer, and Systems Engineering
Rensselaer Polytechnic Institute, Troy, NY
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